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| author | Bernhard Beschow <shentey@gmail.com> | 2023-10-07 14:38:20 +0200 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2023-10-22 05:18:17 -0400 |
| commit | 6fe4464c05f45e726fcfa4a7927f4ed27444a0ca (patch) | |
| tree | cd670f30624899f2c54c572bcb38e99e06ff2172 /include/hw/southbridge/piix.h | |
| parent | e47e5a5b79ffd6b3ca72ea383e3c756b68402735 (diff) | |
| download | focaccia-qemu-6fe4464c05f45e726fcfa4a7927f4ed27444a0ca.tar.gz focaccia-qemu-6fe4464c05f45e726fcfa4a7927f4ed27444a0ca.zip | |
hw/isa/piix3: Create USB controller in host device
The USB controller is an integral part of PIIX3 (function 2). So create it as part of the south bridge. Note that the USB function is optional in QEMU. This is why it gets object_initialize_child()'ed in realize rather than in instance_init. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231007123843.127151-13-shentey@gmail.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'include/hw/southbridge/piix.h')
| -rw-r--r-- | include/hw/southbridge/piix.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 1daeff397c..5cd866f1f2 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -15,6 +15,7 @@ #include "hw/pci/pci_device.h" #include "hw/ide/pci.h" #include "hw/rtc/mc146818rtc.h" +#include "hw/usb/hcd-uhci.h" /* PIRQRC[A:D]: PIRQx Route Control Registers */ #define PIIX_PIRQCA 0x60 @@ -54,12 +55,15 @@ struct PIIXState { MC146818RtcState rtc; PCIIDEState ide; + UHCIState uhci; /* Reset Control Register contents */ uint8_t rcr; /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */ MemoryRegion rcr_mem; + + bool has_usb; }; typedef struct PIIXState PIIX3State; |