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authorCédric Le Goater <clg@kaod.org>2021-10-12 08:20:08 +0200
committerCédric Le Goater <clg@kaod.org>2021-10-12 08:20:08 +0200
commita779e37c681f17f83e1d31a68c030731ebc8c998 (patch)
tree3931a0714e1dad7be2d132ace6421ab840e56fe4 /include/hw/ssi/aspeed_smc.h
parent71255c48e7b902483b94862f4882ddd050fe8ad8 (diff)
downloadfocaccia-qemu-a779e37c681f17f83e1d31a68c030731ebc8c998.tar.gz
focaccia-qemu-a779e37c681f17f83e1d31a68c030731ebc8c998.zip
aspeed/smc: Introduce a new addr_width() class handler
The AST2400 SPI controller has a transitional HW interface and it
stores the address width currently in use in a different register than
all the other SMC controllers. It needs special handling when working
in 4B mode.

Make it clear through a class handler. This also removes another use
of the segments array.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'include/hw/ssi/aspeed_smc.h')
-rw-r--r--include/hw/ssi/aspeed_smc.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h
index a1ca0e65c4..8dc8129498 100644
--- a/include/hw/ssi/aspeed_smc.h
+++ b/include/hw/ssi/aspeed_smc.h
@@ -111,6 +111,7 @@ struct AspeedSMCClass {
     void (*reg_to_segment)(const AspeedSMCState *s, uint32_t reg,
                            AspeedSegments *seg);
     void (*dma_ctrl)(AspeedSMCState *s, uint32_t value);
+    int (*addr_width)(const AspeedSMCState *s);
 };
 
 #endif /* ASPEED_SMC_H */