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authorPeter Maydell <peter.maydell@linaro.org>2016-06-17 15:23:47 +0100
committerPeter Maydell <peter.maydell@linaro.org>2016-06-17 15:23:51 +0100
commitb1a0eb777d9304ad69c577d5fdd8e20e4bf5644f (patch)
tree9d0ca8f7f1fa404bb28f0849d8ef1b2a5bbb9091 /include/hw/timer/aspeed_timer.h
parentf7b9358e2cf12a5eb07f5f9301fdadc932f9ee03 (diff)
downloadfocaccia-qemu-b1a0eb777d9304ad69c577d5fdd8e20e4bf5644f.tar.gz
focaccia-qemu-b1a0eb777d9304ad69c577d5fdd8e20e4bf5644f.zip
hw/intc/arm_gicv3: Implement CPU i/f SGI generation registers
Implement the registers in the GICv3 CPU interface which generate
new SGI interrupts.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
Tested-by: Shannon Zhao <shannon.zhao@linaro.org>
Message-id: 1465915112-29272-18-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'include/hw/timer/aspeed_timer.h')
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