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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-02-21 17:10:09 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-03-01 17:07:59 -0800 |
| commit | b8e1f32cda7805236c2bd497106a9356431c2d60 (patch) | |
| tree | 9371f41a7a6c5c75c37b9998024eb8c32d7ef7e2 /include/hw/xen/interface/sched.h | |
| parent | b7fa70e2afa6c784f21f749572ce78f6467666fd (diff) | |
| download | focaccia-qemu-b8e1f32cda7805236c2bd497106a9356431c2d60.tar.gz focaccia-qemu-b8e1f32cda7805236c2bd497106a9356431c2d60.zip | |
target/riscv: Add support for Zicond extension
The spec can be found in https://github.com/riscv/riscv-zicond. Two instructions are added: - czero.eqz: Moves zero to a register rd, if the condition rs2 is equal to zero, otherwise moves rs1 to rd. - czero.nez: Moves zero to a register rd, if the condition rs2 is nonzero, otherwise moves rs1 to rd. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-ID: <20230221091009.36545-1-liweiwei@iscas.ac.cn> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'include/hw/xen/interface/sched.h')
0 files changed, 0 insertions, 0 deletions