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authorPhilippe Mathieu-Daudé <philmd@linaro.org>2023-10-24 18:24:20 +0200
committerCédric Le Goater <clg@kaod.org>2023-10-25 09:52:44 +0200
commita0c21030705246fc53703253d9b9fccd88aa88d0 (patch)
tree1ef7f67336cc104f87b72f289ee078a7dbfde513 /include/hw
parent24a88476ffbecdd6ffb96a5298d90de10176a301 (diff)
downloadfocaccia-qemu-a0c21030705246fc53703253d9b9fccd88aa88d0.tar.gz
focaccia-qemu-a0c21030705246fc53703253d9b9fccd88aa88d0.zip
hw/arm/aspeed: Move AspeedSoCState::armv7m to Aspeed10x0SoCState
The v7-M core is specific to the Aspeed 10x0 series,
remove it from the common AspeedSoCState.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'include/hw')
-rw-r--r--include/hw/arm/aspeed_soc.h5
1 files changed, 2 insertions, 3 deletions
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index ee7926b81c..2118a441f7 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -47,13 +47,10 @@
 #define ASPEED_JTAG_NUM  2
 
 struct AspeedSoCState {
-    /*< private >*/
     DeviceState parent;
 
-    /*< public >*/
     ARMCPU cpu[ASPEED_CPUS_NUM];
     A15MPPrivState     a7mpcore;
-    ARMv7MState        armv7m;
     MemoryRegion *memory;
     MemoryRegion *dram_mr;
     MemoryRegion dram_container;
@@ -117,6 +114,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)
 
 struct Aspeed10x0SoCState {
     AspeedSoCState parent;
+
+    ARMv7MState armv7m;
 };
 
 #define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"