diff options
| author | Bharata B Rao <bharata@linux.ibm.com> | 2019-12-19 08:44:44 +0530 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2020-01-08 11:01:59 +1100 |
| commit | 50fd0c375bef09d22b6828972c4ed4f945c95ed8 (patch) | |
| tree | 5962be76fdcafe78633b7420d2b2a1b823182b63 /include/standard-headers/drm/drm_fourcc.h | |
| parent | bc5fdfc0a1377418902e215f8d7be00e46b9ac9c (diff) | |
| download | focaccia-qemu-50fd0c375bef09d22b6828972c4ed4f945c95ed8.tar.gz focaccia-qemu-50fd0c375bef09d22b6828972c4ed4f945c95ed8.zip | |
linux-headers: Update
Update to mainline commit: d1eef1c61974 ("Linux 5.5-rc2")
Signed-off-by: Bharata B Rao <bharata@linux.ibm.com>
Message-Id: <20191219031445.8949-2-bharata@linux.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'include/standard-headers/drm/drm_fourcc.h')
| -rw-r--r-- | include/standard-headers/drm/drm_fourcc.h | 28 |
1 files changed, 26 insertions, 2 deletions
diff --git a/include/standard-headers/drm/drm_fourcc.h b/include/standard-headers/drm/drm_fourcc.h index a308c91b4f..46d279f515 100644 --- a/include/standard-headers/drm/drm_fourcc.h +++ b/include/standard-headers/drm/drm_fourcc.h @@ -68,7 +68,7 @@ extern "C" { #define fourcc_code(a, b, c, d) ((uint32_t)(a) | ((uint32_t)(b) << 8) | \ ((uint32_t)(c) << 16) | ((uint32_t)(d) << 24)) -#define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */ +#define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */ /* Reserve 0 for the invalid format specifier */ #define DRM_FORMAT_INVALID 0 @@ -647,7 +647,21 @@ extern "C" { * Further information on the use of AFBC modifiers can be found in * Documentation/gpu/afbc.rst */ -#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) fourcc_mod_code(ARM, __afbc_mode) + +/* + * The top 4 bits (out of the 56 bits alloted for specifying vendor specific + * modifiers) denote the category for modifiers. Currently we have only two + * categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen + * different categories. + */ +#define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \ + fourcc_mod_code(ARM, ((uint64_t)(__type) << 52) | ((__val) & 0x000fffffffffffffULL)) + +#define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00 +#define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01 + +#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \ + DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode) /* * AFBC superblock size @@ -742,6 +756,16 @@ extern "C" { #define AFBC_FORMAT_MOD_BCH (1ULL << 11) /* + * Arm 16x16 Block U-Interleaved modifier + * + * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image + * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels + * in the block are reordered. + */ +#define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \ + DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL) + +/* * Allwinner tiled modifier * * This tiling mode is implemented by the VPU found on all Allwinner platforms, |