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| author | Vivek Goyal <vgoyal@redhat.com> | 2022-02-08 15:48:05 -0500 |
|---|---|---|
| committer | Dr. David Alan Gilbert <dgilbert@redhat.com> | 2022-02-17 17:21:45 +0000 |
| commit | ef17dd6a8e6b6e3aeb29233996d44dfcb736d515 (patch) | |
| tree | 41fe944078af9da25e79e8194dea8f8e8ef3e606 /include/standard-headers/drm/drm_fourcc.h | |
| parent | a086d54c6ffa38f7e71f182b63a25315304a3392 (diff) | |
| download | focaccia-qemu-ef17dd6a8e6b6e3aeb29233996d44dfcb736d515.tar.gz focaccia-qemu-ef17dd6a8e6b6e3aeb29233996d44dfcb736d515.zip | |
linux-headers: Update headers to v5.17-rc1
Update headers to 5.17-rc1. I need latest fuse changes. Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Vivek Goyal <vgoyal@redhat.com> Message-Id: <20220208204813.682906-3-vgoyal@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Diffstat (limited to 'include/standard-headers/drm/drm_fourcc.h')
| -rw-r--r-- | include/standard-headers/drm/drm_fourcc.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/include/standard-headers/drm/drm_fourcc.h b/include/standard-headers/drm/drm_fourcc.h index 2c025cb4fe..4888f85f69 100644 --- a/include/standard-headers/drm/drm_fourcc.h +++ b/include/standard-headers/drm/drm_fourcc.h @@ -313,6 +313,13 @@ extern "C" { */ #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */ +/* 2 plane YCbCr420. + * 3 10 bit components and 2 padding bits packed into 4 bytes. + * index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian + * index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0 [2:10:10:10:2:10:10:10] little endian + */ +#define DRM_FORMAT_P030 fourcc_code('P', '0', '3', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel packed */ + /* 3 plane non-subsampled (444) YCbCr * 16 bits per component, but only 10 bits are used and 6 bits are padded * index 0: Y plane, [15:0] Y:x [10:6] little endian @@ -853,6 +860,10 @@ drm_fourcc_canonicalize_nvidia_format_mod(uint64_t modifier) * and UV. Some SAND-using hardware stores UV in a separate tiled * image from Y to reduce the column height, which is not supported * with these modifiers. + * + * The DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT modifier is also + * supported for DRM_FORMAT_P030 where the columns remain as 128 bytes + * wide, but as this is a 10 bpp format that translates to 96 pixels. */ #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \ |