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authorZhenzhong Duan <zhenzhong.duan@intel.com>2024-03-20 17:31:38 +0800
committerPaolo Bonzini <pbonzini@redhat.com>2024-04-23 17:35:25 +0200
commitc895fa54e3060c5ac6f3888dce96c9b78626072b (patch)
tree916afe7c75fde197d82b9ea9df03c5d4e4cc5823 /include/standard-headers/linux/input-event-codes.h
parenta5acf4f26c208a05d05ef1bde65553ce2ab5e5d0 (diff)
downloadfocaccia-qemu-c895fa54e3060c5ac6f3888dce96c9b78626072b.tar.gz
focaccia-qemu-c895fa54e3060c5ac6f3888dce96c9b78626072b.zip
target/i386: Introduce Icelake-Server-v7 to enable TSX
When start L2 guest with both L1/L2 using Icelake-Server-v3 or above,
QEMU reports below warning:

"warning: host doesn't support requested feature: MSR(10AH).taa-no [bit 8]"

Reason is QEMU Icelake-Server-v3 has TSX feature disabled but enables taa-no
bit. It's meaningless that TSX isn't supported but still claim TSX is secure.
So L1 KVM doesn't expose taa-no to L2 if TSX is unsupported, then starting L2
triggers the warning.

Fix it by introducing a new version Icelake-Server-v7 which has both TSX
and taa-no features. Then guest can use TSX securely when it see taa-no.

This matches the production Icelake which supports TSX and isn't susceptible
to TSX Async Abort (TAA) vulnerabilities, a.k.a, taa-no.

Ideally, TSX should have being enabled together with taa-no since v3, but for
compatibility, we'd better to add v7 to enable it.

Fixes: d965dc35592d ("target/i386: Add ARCH_CAPABILITIES related bits into Icelake-Server CPU model")
Tested-by: Xiangfei Ma <xiangfeix.ma@intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Message-ID: <20240320093138.80267-2-zhenzhong.duan@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'include/standard-headers/linux/input-event-codes.h')
0 files changed, 0 insertions, 0 deletions