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| author | Peter Maydell <peter.maydell@linaro.org> | 2017-11-21 09:56:05 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-11-21 09:56:05 +0000 |
| commit | 5f49d73cb3c571e1503b86a9014d2908b2036d03 (patch) | |
| tree | 594ba8452abeeaf3a4a0765e80c1ce115fd9ecfe /include | |
| parent | 3da87f771311199e9b915163315ba0e9b96c6d1b (diff) | |
| parent | b350ae138fcb062f49904f5115cc5fe188a02906 (diff) | |
| download | focaccia-qemu-5f49d73cb3c571e1503b86a9014d2908b2036d03.tar.gz focaccia-qemu-5f49d73cb3c571e1503b86a9014d2908b2036d03.zip | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20171120' into staging
target-arm queue: * hw/arm: Silence xlnx-ep108 deprecation warning during tests * hw/arm/aspeed: Unlock SCU when running kernel * arm: check regime, not current state, for ATS write PAR format * nvic: Fix ARMv7M MPU_RBAR reads * target/arm: Report GICv3 sysregs present in ID registers if needed # gpg: Signature made Mon 20 Nov 2017 17:35:25 GMT # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20171120: hw/arm: Silence xlnx-ep108 deprecation warning during tests hw/arm/aspeed: Unlock SCU when running kernel arm: check regime, not current state, for ATS write PAR format nvic: Fix ARMv7M MPU_RBAR reads target/arm: Report GICv3 sysregs present in ID registers if needed Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/misc/aspeed_scu.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h index bd4ac013f9..d70cc0aeca 100644 --- a/include/hw/misc/aspeed_scu.h +++ b/include/hw/misc/aspeed_scu.h @@ -29,6 +29,7 @@ typedef struct AspeedSCUState { uint32_t silicon_rev; uint32_t hw_strap1; uint32_t hw_strap2; + uint32_t hw_prot_key; } AspeedSCUState; #define AST2400_A0_SILICON_REV 0x02000303U @@ -38,6 +39,8 @@ typedef struct AspeedSCUState { extern bool is_supported_silicon_rev(uint32_t silicon_rev); +#define ASPEED_SCU_PROT_KEY 0x1688A8A8 + /* * Extracted from Aspeed SDK v00.03.21. Fixes and extra definitions * were added. |