Merge tag 'qemu-sparc-20240213' of https://github.com/mcayland/qemu into staging

qemu-sparc queue

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# gpg: Signature made Tue 13 Feb 2024 19:37:48 GMT
# gpg:                using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F
# gpg:                issuer "mark.cave-ayland@ilande.co.uk"
# gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" [full]
# Primary key fingerprint: CC62 1AB9 8E82 200D 915C  C9C4 5BC2 C56F AE0F 321F

* tag 'qemu-sparc-20240213' of https://github.com/mcayland/qemu: (88 commits)
  esp.c: add my copyright to the file
  esp.c: switch TypeInfo registration to use DEFINE_TYPES() macro
  esp.c: keep track of the DRQ state during DMA
  esp.c: rename irq_data IRQ to drq_irq
  esp.c: implement DMA Transfer Pad command for DATA phases
  esp.c: replace n variable with len in esp_do_nodma()
  esp.c: consolidate DMA and PDMA logic in STATUS and MESSAGE IN phases
  esp.c: remove redundant n variable in PDMA COMMAND phase
  esp.c: consolidate DMA and PDMA logic in MESSAGE OUT phase
  esp.c: consolidate DMA and PDMA logic in DATA IN phase
  esp.c: consolidate DMA and PDMA logic in DATA OUT phase
  esp.c: only transfer non-DMA MESSAGE OUT phase data for specific commands
  esp.c: only transfer non-DMA COMMAND phase data for specific commands
  esp.c: improve ESP_RSEQ logic consolidation
  esp.c: handle non-DMA FIFO writes used to terminate DMA commands
  esp.c: remove restriction on FIFO read access when DMA memory routines defined
  esp.c: handle TC underflow for DMA SCSI requests
  esp.c: don't clear the SCSI phase when reading ESP_RINTR
  esp.c: ensure that STAT_INT is cleared when reading ESP_RINTR
  esp.c: consolidate end of command sequence after ICCS command
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

1 files changed, 5 insertions, 13 deletions

diff --git a/include/hw/scsi/esp.h b/include/hw/scsi/esp.h
index 13b17496f8..533d856aa3 100644
--- a/include/hw/scsi/esp.h
+++ b/include/hw/scsi/esp.h
@@ -25,7 +25,8 @@ struct ESPState {
     uint8_t rregs[ESP_REGS];
     uint8_t wregs[ESP_REGS];
     qemu_irq irq;
-    qemu_irq irq_data;
+    qemu_irq drq_irq;
+    bool drq_state;
     uint8_t chip_id;
     bool tchi_written;
     int32_t ti_size;
@@ -40,8 +41,7 @@ struct ESPState {
     uint8_t lun;
     uint32_t do_cmd;
 
-    bool data_in_ready;
-    uint8_t ti_cmd;
+    bool data_ready;
     int dma_enabled;
 
     uint32_t async_len;
@@ -51,7 +51,6 @@ struct ESPState {
     ESPDMAMemoryReadWriteFunc dma_memory_write;
     void *dma_opaque;
     void (*dma_cb)(ESPState *s);
-    uint8_t pdma_cb;
 
     uint8_t mig_version_id;
 
@@ -63,6 +62,8 @@ struct ESPState {
     uint8_t mig_ti_buf[ESP_FIFO_SZ];
     uint8_t mig_cmdbuf[ESP_CMDFIFO_SZ];
     uint32_t mig_cmdlen;
+
+    uint8_t mig_ti_cmd;
 };
 
 #define TYPE_SYSBUS_ESP "sysbus-esp"
@@ -150,15 +151,6 @@ struct SysBusESPState {
 #define TCHI_FAS100A 0x4
 #define TCHI_AM53C974 0x12
 
-/* PDMA callbacks */
-enum pdma_cb {
-    SATN_PDMA_CB = 0,
-    S_WITHOUT_SATN_PDMA_CB = 1,
-    SATN_STOP_PDMA_CB = 2,
-    WRITE_RESPONSE_PDMA_CB = 3,
-    DO_DMA_PDMA_CB = 4
-};
-
 void esp_dma_enable(ESPState *s, int irq, int level);
 void esp_request_cancelled(SCSIRequest *req);
 void esp_command_complete(SCSIRequest *req, size_t resid);