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| author | Jackson Donaldson <jackson88044@gmail.com> | 2025-07-04 18:32:31 -0400 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2025-07-08 17:31:38 +0100 |
| commit | 65714d3e6c384956537c43ee9a58f2e4ebfdd883 (patch) | |
| tree | 617d141e3c561bcbea2d61114eb7fec8d1250b68 /include | |
| parent | 3ec680e64c6d0686c518f25fdadf8866d7cd12a1 (diff) | |
| download | focaccia-qemu-65714d3e6c384956537c43ee9a58f2e4ebfdd883.tar.gz focaccia-qemu-65714d3e6c384956537c43ee9a58f2e4ebfdd883.zip | |
MAX78000: Add ICC to SOC
This commit adds the instruction cache controller to max78000_soc Signed-off-by: Jackson Donaldson <jcksn@duck.com> Reviewed-by: Peter Maydell <petermaydell@linaro.org> Message-id: 20250704223239.248781-4-jcksn@duck.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/arm/max78000_soc.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/hw/arm/max78000_soc.h b/include/hw/arm/max78000_soc.h index 97bf4099c9..27b506d6ee 100644 --- a/include/hw/arm/max78000_soc.h +++ b/include/hw/arm/max78000_soc.h @@ -11,6 +11,7 @@ #include "hw/or-irq.h" #include "hw/arm/armv7m.h" +#include "hw/misc/max78000_icc.h" #include "qom/object.h" #define TYPE_MAX78000_SOC "max78000-soc" @@ -21,6 +22,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(MAX78000State, MAX78000_SOC) #define SRAM_BASE_ADDRESS 0x20000000 #define SRAM_SIZE (128 * 1024) +/* The MAX78k has 2 instruction caches; only icc0 matters, icc1 is for RISC */ +#define MAX78000_NUM_ICC 2 + struct MAX78000State { SysBusDevice parent_obj; @@ -29,6 +33,8 @@ struct MAX78000State { MemoryRegion sram; MemoryRegion flash; + Max78000IccState icc[MAX78000_NUM_ICC]; + Clock *sysclk; }; |