Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200123-4' into staging

target-arm queue:
 * fix bug in PAuth emulation
 * add PMU to Cortex-R5, Cortex-R5F
 * qemu-nbd: Convert documentation to rST
 * qemu-block-drivers: Convert documentation to rST
 * Fix Exynos4210 UART DMA support
 * Various minor code cleanups

# gpg: Signature made Thu 23 Jan 2020 16:35:38 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20200123-4:
  hw/arm/exynos4210: Connect serial port DMA busy signals with pl330
  hw/char/exynos4210_uart: Add receive DMA support
  hw/char/exynos4210_uart: Implement Rx FIFO level triggers and timeouts
  hw/char/exynos4210_uart: Implement post_load function
  hw/char/exynos4210_uart: Convert to support tracing
  hw/arm/exynos4210: Fix DMA initialization
  hw/core/or-irq: Increase limit of or-lines to 48
  dma/pl330: Convert to support tracing
  hw/misc/stm32f4xx_syscfg: Fix copy/paste error
  target/arm/arch_dump: Add SVE notes
  qemu-block-drivers: Convert to rST
  docs: Create stub system manual
  qemu-nbd: Convert invocation documentation to rST
  hw/arm: Use helper function to trigger hotplug handler plug
  hw/acpi: Remove extra indent in ACPI GED hotplug cb
  tests/tcg/aarch64: Add pauth-4
  tests/tcg/aarch64: Add pauth-3
  tests/tcg/aarch64: Fix compilation parameters for pauth-%
  target/arm: Fix PAuth sbox functions
  target/arm: add PMU feature to cortex-r5 and cortex-r5f

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

3 files changed, 6 insertions, 1 deletions

diff --git a/include/elf.h b/include/elf.h
index 3501e0c8d0..8fbfe60e09 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -1650,6 +1650,7 @@ typedef struct elf64_shdr {
 #define NT_ARM_HW_BREAK 0x402           /* ARM hardware breakpoint registers */
 #define NT_ARM_HW_WATCH 0x403           /* ARM hardware watchpoint registers */
 #define NT_ARM_SYSTEM_CALL      0x404   /* ARM system call number */
+#define NT_ARM_SVE      0x405           /* ARM Scalable Vector Extension regs */
 
 /*
  * Physical entry point into the kernel.
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index f0f23b0e9b..55260394af 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -24,6 +24,7 @@
 #ifndef EXYNOS4210_H
 #define EXYNOS4210_H
 
+#include "hw/or-irq.h"
 #include "hw/sysbus.h"
 #include "target/arm/cpu-qom.h"
 
@@ -74,6 +75,8 @@
 
 #define EXYNOS4210_I2C_NUMBER               9
 
+#define EXYNOS4210_NUM_DMA      3
+
 typedef struct Exynos4210Irq {
     qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
     qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ];
@@ -97,6 +100,7 @@ typedef struct Exynos4210State {
     MemoryRegion boot_secondary;
     MemoryRegion bootreg_mem;
     I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
+    qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA];
 } Exynos4210State;
 
 #define TYPE_EXYNOS4210_SOC "exynos4210"
diff --git a/include/hw/or-irq.h b/include/hw/or-irq.h
index 3a3230dd84..0038bfbe3d 100644
--- a/include/hw/or-irq.h
+++ b/include/hw/or-irq.h
@@ -33,7 +33,7 @@
 /* This can safely be increased if necessary without breaking
  * migration compatibility (as long as it remains greater than 15).
  */
-#define MAX_OR_LINES      32
+#define MAX_OR_LINES      48
 
 typedef struct OrIRQState qemu_or_irq;