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| author | Luc Michel <luc.michel@amd.com> | 2025-09-26 09:07:24 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2025-10-07 10:35:36 +0100 |
| commit | 8aaeb96405d2e4b6593cb9d5d943a54e36cbccbc (patch) | |
| tree | d8d9441692a3b74917ff6cc3210d2150c8dc3ccf /include | |
| parent | b392177e42e25b076104eb8fe3a484a9a16642c7 (diff) | |
| download | focaccia-qemu-8aaeb96405d2e4b6593cb9d5d943a54e36cbccbc.tar.gz focaccia-qemu-8aaeb96405d2e4b6593cb9d5d943a54e36cbccbc.zip | |
hw/arm/xlnx-versal: gem: refactor creation
Refactor the GEM ethernet controllers creation using the VersalMap structure. Note that the connection to the CRL is removed for now and will be re-added by next commits. The FDT nodes are created in reverse order compared to the devices creation to keep backward compatibility with the previous generated FDTs. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-7-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/arm/xlnx-versal.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index 4a7a2d85aa..1fcc2b623d 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -18,7 +18,6 @@ #include "hw/or-irq.h" #include "hw/intc/arm_gicv3.h" #include "hw/dma/xlnx-zdma.h" -#include "hw/net/cadence_gem.h" #include "hw/rtc/xlnx-zynqmp-rtc.h" #include "qom/object.h" #include "hw/usb/xlnx-usb-subsystem.h" @@ -78,8 +77,6 @@ struct Versal { MemoryRegion mr_ocm; struct { - CadenceGEMState gem[XLNX_VERSAL_NR_GEMS]; - OrIRQState gem_irq_orgate[XLNX_VERSAL_NR_GEMS]; XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS]; VersalUsb2 usb; } iou; |