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| author | Caleb Schlossin <calebs@linux.vnet.ibm.com> | 2024-02-27 14:36:23 -0600 |
|---|---|---|
| committer | Nicholas Piggin <npiggin@gmail.com> | 2024-03-13 02:47:04 +1000 |
| commit | 9940412ae4ae2d4971959c13311ba8d822974452 (patch) | |
| tree | aeeea6c94ebb348eaa93b57838d40371099cee3f /include | |
| parent | 0b8893236ef11dd26be9290156ea34cb122e4dbe (diff) | |
| download | focaccia-qemu-9940412ae4ae2d4971959c13311ba8d822974452.tar.gz focaccia-qemu-9940412ae4ae2d4971959c13311ba8d822974452.zip | |
ppc/pnv: Improve pervasive topology calculation for big-core
Big (SMT8) cores have a complicated function to map the core, thread ID to pervasive topology (PIR). Fix this for power8, power9, and power10. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Caleb Schlossin <calebs@linux.vnet.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/ppc/pnv_chip.h | 2 | ||||
| -rw-r--r-- | include/hw/ppc/pnv_core.h | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h index af4cd7a8b8..8589f3291e 100644 --- a/include/hw/ppc/pnv_chip.h +++ b/include/hw/ppc/pnv_chip.h @@ -147,7 +147,7 @@ struct PnvChipClass { DeviceRealize parent_realize; - uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); + uint32_t (*chip_pir)(PnvChip *chip, uint32_t core_id, uint32_t thread_id); void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu); void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu); diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h index 4db21229a6..c6d62fd145 100644 --- a/include/hw/ppc/pnv_core.h +++ b/include/hw/ppc/pnv_core.h @@ -36,6 +36,7 @@ struct PnvCore { /*< public >*/ PowerPCCPU **threads; uint32_t pir; + uint32_t hwid; uint64_t hrmor; PnvChip *chip; |