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| author | Peter Maydell <peter.maydell@linaro.org> | 2017-08-04 13:03:58 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-08-04 13:03:58 +0100 |
| commit | c233a35d3d91af666aa95a6a3ba8244d4ce728c6 (patch) | |
| tree | 42a0ae3ab0fb3b6beb861d598dab5d92eee728cf /include | |
| parent | 8377e9f60959dd6e0562cf67027c5c370d7d9f06 (diff) | |
| parent | d673a68db6963e86536b125af464bb6ed03eba33 (diff) | |
| download | focaccia-qemu-c233a35d3d91af666aa95a6a3ba8244d4ce728c6.tar.gz focaccia-qemu-c233a35d3d91af666aa95a6a3ba8244d4ce728c6.zip | |
Merge remote-tracking branch 'remotes/yongbok/tags/mips-20170803' into staging
MIPS patches 2017-08-03 Changes: KVM T&E segment support for TCG malta: leave space for the bootmap after the initrd Apply CP0.PageMask before writing into TLB entry Fix fallout from indirect branch optimisation # gpg: Signature made Thu 03 Aug 2017 15:32:59 BST # gpg: using RSA key 0x2238EB86D5F797C2 # gpg: Good signature from "Yongbok Kim <yongbok.kim@imgtec.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 8600 4CF5 3415 A5D9 4CFA 2B5C 2238 EB86 D5F7 97C2 * remotes/yongbok/tags/mips-20170803: target/mips: Fix RDHWR CC with icount target/mips: Drop redundant gen_io_start/stop() target/mips: Use BS_EXCP where interrupts are expected target-mips: apply CP0.PageMask before writing into TLB entry mips: Add KVM T&E segment support for TCG mips: Improve segment defs for KVM T&E guests mips/malta: leave space for the bootmap after the initrd target-mips: Don't stop on [d]mtc0 DESAVE/KScratch Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/mips/cpudevs.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/include/hw/mips/cpudevs.h b/include/hw/mips/cpudevs.h index 698339b83e..291f59281a 100644 --- a/include/hw/mips/cpudevs.h +++ b/include/hw/mips/cpudevs.h @@ -5,11 +5,12 @@ /* Definitions for MIPS CPU internal devices. */ -/* mips_addr.c */ +/* addr.c */ uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr); uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr); uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr); - +bool mips_um_ksegs_enabled(void); +void mips_um_ksegs_enable(void); /* mips_int.c */ void cpu_mips_irq_init_cpu(MIPSCPU *cpu); |