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| author | Frederic Barrat <fbarrat@linux.ibm.com> | 2024-09-13 11:16:48 -0500 |
|---|---|---|
| committer | Nicholas Piggin <npiggin@gmail.com> | 2024-11-04 09:14:24 +1000 |
| commit | cebfeb9e56859bcac545a2340798e005cfde21cf (patch) | |
| tree | 178788ec38ab92f0e305143ee22cb5f79539c729 /include | |
| parent | b9deafe7bf463fb7c7d7ee713774bfaf785eeb87 (diff) | |
| download | focaccia-qemu-cebfeb9e56859bcac545a2340798e005cfde21cf.tar.gz focaccia-qemu-cebfeb9e56859bcac545a2340798e005cfde21cf.zip | |
ppc/xive2: Support TIMA "Pull OS Context to Odd Thread Reporting Line"
Adds support for single byte writes to offset 0xC18 of the TIMA address space. When this offset is written to, the hardware disables the OS context and copies the current state information to the odd cache line of the pair specified by the NVT structure indexed by the OS CAM entry. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.vnet.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/ppc/xive2.h | 2 | ||||
| -rw-r--r-- | include/hw/ppc/xive2_regs.h | 2 | ||||
| -rw-r--r-- | include/hw/ppc/xive_regs.h | 3 |
3 files changed, 7 insertions, 0 deletions
diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h index ab68f8d157..654f485e9b 100644 --- a/include/hw/ppc/xive2.h +++ b/include/hw/ppc/xive2.h @@ -107,5 +107,7 @@ void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, uint64_t value, unsigned size); uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, unsigned size); +void xive2_tm_pull_os_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned size); #endif /* PPC_XIVE2_H */ diff --git a/include/hw/ppc/xive2_regs.h b/include/hw/ppc/xive2_regs.h index 4349d009d0..7acf7dccf3 100644 --- a/include/hw/ppc/xive2_regs.h +++ b/include/hw/ppc/xive2_regs.h @@ -171,7 +171,9 @@ typedef struct Xive2Nvp { #define NVP2_W5_VP_END_BLOCK PPC_BITMASK32(4, 7) #define NVP2_W5_VP_END_INDEX PPC_BITMASK32(8, 31) uint32_t w6; +#define NVP2_W6_REPORTING_LINE PPC_BITMASK32(4, 31) uint32_t w7; +#define NVP2_W7_REPORTING_LINE PPC_BITMASK32(0, 23) } Xive2Nvp; #define xive2_nvp_is_valid(nvp) (be32_to_cpu((nvp)->w0) & NVP2_W0_VALID) diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h index 9062c6abf6..27a744d50d 100644 --- a/include/hw/ppc/xive_regs.h +++ b/include/hw/ppc/xive_regs.h @@ -77,6 +77,7 @@ #define TM_LSMFB 0x3 /* - + + + */ #define TM_ACK_CNT 0x4 /* - + - - */ #define TM_INC 0x5 /* - + - + */ +#define TM_LGS 0x5 /* + + + + */ /* Rename P10 */ #define TM_AGE 0x6 /* - + - + */ #define TM_PIPR 0x7 /* - + - + */ #define TM_OGEN 0xF /* - + - - */ /* P10 only */ @@ -129,6 +130,8 @@ #define TM_SPC_PULL_USR_CTX_OL 0xc08 /* Store8 Pull/Inval usr ctx to odd */ /* line */ #define TM_SPC_ACK_OS_EL 0xc10 /* Store8 ack OS irq to even line */ +#define TM_SPC_PULL_OS_CTX_OL 0xc18 /* Pull/Invalidate OS context to */ + /* odd Thread reporting line */ #define TM_SPC_ACK_HV_POOL_EL 0xc20 /* Store8 ack HV evt pool to even */ /* line */ #define TM_SPC_ACK_HV_EL 0xc30 /* Store8 ack HV irq to even line */ |