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| author | Gustavo Romero <gustavo.romero@linaro.org> | 2024-07-05 09:40:42 +0100 |
|---|---|---|
| committer | Alex Bennée <alex.bennee@linaro.org> | 2024-07-05 12:35:14 +0100 |
| commit | bef6a77f6da8bdba7dca36aec4976b434d0d8f1c (patch) | |
| tree | de074abcdd809290c7f73e2679c27a8944e21523 /linux-user/aarch64/target_prctl.h | |
| parent | 0c9b437c90b127bb99fc2e0d3cd41136b2148078 (diff) | |
| download | focaccia-qemu-bef6a77f6da8bdba7dca36aec4976b434d0d8f1c.tar.gz focaccia-qemu-bef6a77f6da8bdba7dca36aec4976b434d0d8f1c.zip | |
target/arm: Factor out code for setting MTE TCF0 field
Factor out the code used for setting the MTE TCF0 field from the prctl code into a convenient function. Other subsystems, like gdbstub, need to set this field as well, so keep it as a separate function to avoid duplication and ensure consistency in how this field is set across the board. Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Message-Id: <20240628050850.536447-7-gustavo.romero@linaro.org> [AJB: clean-up includes, move MTE defines] Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240705084047.857176-36-alex.bennee@linaro.org>
Diffstat (limited to 'linux-user/aarch64/target_prctl.h')
| -rw-r--r-- | linux-user/aarch64/target_prctl.h | 22 |
1 files changed, 2 insertions, 20 deletions
diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h index aa8e203c15..ed75b9e4b5 100644 --- a/linux-user/aarch64/target_prctl.h +++ b/linux-user/aarch64/target_prctl.h @@ -7,6 +7,7 @@ #define AARCH64_TARGET_PRCTL_H #include "target/arm/cpu-features.h" +#include "mte_user_helper.h" static abi_long do_prctl_sve_get_vl(CPUArchState *env) { @@ -173,26 +174,7 @@ static abi_long do_prctl_set_tagged_addr_ctrl(CPUArchState *env, abi_long arg2) env->tagged_addr_enable = arg2 & PR_TAGGED_ADDR_ENABLE; if (cpu_isar_feature(aa64_mte, cpu)) { - /* - * Write PR_MTE_TCF to SCTLR_EL1[TCF0]. - * - * The kernel has a per-cpu configuration for the sysadmin, - * /sys/devices/system/cpu/cpu<N>/mte_tcf_preferred, - * which qemu does not implement. - * - * Because there is no performance difference between the modes, and - * because SYNC is most useful for debugging MTE errors, choose SYNC - * as the preferred mode. With this preference, and the way the API - * uses only two bits, there is no way for the program to select - * ASYMM mode. - */ - unsigned tcf = 0; - if (arg2 & PR_MTE_TCF_SYNC) { - tcf = 1; - } else if (arg2 & PR_MTE_TCF_ASYNC) { - tcf = 2; - } - env->cp15.sctlr_el[1] = deposit64(env->cp15.sctlr_el[1], 38, 2, tcf); + arm_set_mte_tcf0(env, arg2); /* * Write PR_MTE_TAG to GCR_EL1[Exclude]. |