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| author | Peter Maydell <peter.maydell@linaro.org> | 2025-06-05 15:18:01 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2025-06-16 11:26:25 +0100 |
| commit | cd38e638c43e4d5d3fd65dd4529c2e6153c9c408 (patch) | |
| tree | d9ce7cdbd85e0d9c351110ca7bc3c1d35e2401ae /linux-user/arm/cpu_loop.c | |
| parent | 6559e7ad8e535b70e34c79076e6cb6c09d626d0d (diff) | |
| download | focaccia-qemu-cd38e638c43e4d5d3fd65dd4529c2e6153c9c408.tar.gz focaccia-qemu-cd38e638c43e4d5d3fd65dd4529c2e6153c9c408.zip | |
hw/arm/mps2: Configure the AN500 CPU with 16 MPU regions
The AN500 application note documents that it configures the Cortex-M7 CPU to have 16 MPU regions. We weren't doing this in our emulation, so the CPU had only the default 8 MPU regions. Set the mpu-ns-regions property to 16 for this board. This bug doesn't affect any of the other board types we model in this source file, because they all use either the Cortex-M3 or Cortex-M4. Those CPUs do not have an RTL configurable number of MPU regions, and always provide 8 regions if the MPU is built in. Cc: qemu-stable@nongnu.org Reported-by: Corentin GENDRE <cocotroupe20@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20250605141801.1083266-1-peter.maydell@linaro.org
Diffstat (limited to 'linux-user/arm/cpu_loop.c')
0 files changed, 0 insertions, 0 deletions