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| author | Richard Henderson <rth@twiddle.net> | 2011-05-20 13:30:00 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@anchor.twiddle.net> | 2011-05-31 10:18:05 -0700 |
| commit | 129d8aa575b1a0c06b471a506c5a233bd270bff4 (patch) | |
| tree | 80a718be1e055815aa3af84695e9c1bcb8ff87bb /linux-user/main.c | |
| parent | 508b43eaf3dd179363557bf68e911ddea637e58b (diff) | |
| download | focaccia-qemu-129d8aa575b1a0c06b471a506c5a233bd270bff4.tar.gz focaccia-qemu-129d8aa575b1a0c06b471a506c5a233bd270bff4.zip | |
target-alpha: Rationalize internal processor registers.
Delete all the code that tried to emulate the real IPRs of some unnamed CPU. Replace those with just 3 slots that we can use to communicate trap information between the helper functions that signal exceptions and the OS trap handler. Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'linux-user/main.c')
| -rw-r--r-- | linux-user/main.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/linux-user/main.c b/linux-user/main.c index 088def3cfd..095459144b 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -2524,9 +2524,9 @@ void cpu_loop (CPUState *env) env->lock_addr = -1; info.si_signo = TARGET_SIGSEGV; info.si_errno = 0; - info.si_code = (page_get_flags(env->ipr[IPR_EXC_ADDR]) & PAGE_VALID + info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR); - info._sifields._sigfault._addr = env->ipr[IPR_EXC_ADDR]; + info._sifields._sigfault._addr = env->trap_arg0; queue_signal(env, info.si_signo, &info); break; case EXCP_DTB_MISS_PAL: @@ -2550,7 +2550,7 @@ void cpu_loop (CPUState *env) info.si_signo = TARGET_SIGBUS; info.si_errno = 0; info.si_code = TARGET_BUS_ADRALN; - info._sifields._sigfault._addr = env->ipr[IPR_EXC_ADDR]; + info._sifields._sigfault._addr = env->trap_arg0; queue_signal(env, info.si_signo, &info); break; case EXCP_OPCDEC: |