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authorAlistair Francis <alistair.francis@wdc.com>2020-11-05 18:32:19 -0800
committerAlistair Francis <alistair.francis@wdc.com>2020-11-09 15:09:53 -0800
commit96338fefc19a143abdc91f6c44f37683274b08d4 (patch)
treea3c4041d35c35abd7726e4b72ca00ab4dcc0b7be /linux-user/main.c
parent7687537ab0c16e0b1e69e7707456573a64b8e13b (diff)
downloadfocaccia-qemu-96338fefc19a143abdc91f6c44f37683274b08d4.tar.gz
focaccia-qemu-96338fefc19a143abdc91f6c44f37683274b08d4.zip
hw/intc/ibex_plic: Clear the claim register when read
After claiming the interrupt by reading the claim register we want to
clear the register to make sure the interrupt doesn't appear at the next
read.

This matches the documentation for the claim register as when an interrupt
is claimed by a target the relevant bit of IP is cleared (which we already
do): https://docs.opentitan.org/hw/ip/rv_plic/doc/index.html

This also matches the current hardware.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 68d4575deef2559b7a747f3bda193fcf43af4558.1604629928.git.alistair.francis@wdc.com
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