diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2021-01-15 13:22:54 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-01-15 13:22:54 +0000 |
| commit | 256af05f52b5f944482341273a77511089d64435 (patch) | |
| tree | 265ec7f999f198eb476a9c56766584c7703268d4 /linux-user/mips/cpu_loop.c | |
| parent | 7c79721606be11b5bc556449e5bcbc331ef6867d (diff) | |
| parent | cd669e20516fad3d8154629f67d4b6caede9b381 (diff) | |
| download | focaccia-qemu-256af05f52b5f944482341273a77511089d64435.tar.gz focaccia-qemu-256af05f52b5f944482341273a77511089d64435.zip | |
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/mips-20210114' into staging
MIPS patches queue - Simplify CPU/ISA definitions - Various maintenance code movements in translate.c - Convert part of the MSA ASE instructions to decodetree - Convert some instructions removed from Release 6 to decodetree - Remove deprecated 'fulong2e' machine alias # gpg: Signature made Thu 14 Jan 2021 16:16:29 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * remotes/philmd-gitlab/tags/mips-20210114: (69 commits) docs/system: Remove deprecated 'fulong2e' machine alias target/mips: Remove vendor specific CPU definitions target/mips: Remove CPU_NANOMIPS32 definition target/mips: Remove CPU_R5900 definition target/mips: Convert Rel6 LL/SC opcodes to decodetree target/mips: Convert Rel6 LLD/SCD opcodes to decodetree target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetree target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetree target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree target/mips: Convert Rel6 COP1X opcode to decodetree target/mips: Convert Rel6 Special2 opcode to decodetree target/mips: Remove now unreachable LSA/DLSA opcodes code target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes target/mips: Extract LSA/DLSA translation generators target/mips: Use decode_ase_msa() generated from decodetree target/mips: Introduce decode tree bindings for MSA ASE target/mips: Pass TCGCond argument to MSA gen_check_zero_element() target/mips: Extract MSA translation routines ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'linux-user/mips/cpu_loop.c')
| -rw-r--r-- | linux-user/mips/cpu_loop.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index cfe7ba5c47..9d813ece4e 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -23,6 +23,7 @@ #include "cpu_loop-common.h" #include "elf.h" #include "internal.h" +#include "fpu_helper.h" # ifdef TARGET_ABI_MIPSO32 # define MIPS_SYSCALL_NUMBER_UNUSED -1 @@ -384,10 +385,8 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) prog_req.frdefault &= interp_req.frdefault; prog_req.fre &= interp_req.fre; - bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS32R2 || - env->insn_flags & ISA_MIPS64R2 || - env->insn_flags & ISA_MIPS32R6 || - env->insn_flags & ISA_MIPS64R6; + bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS_R2 || + env->insn_flags & ISA_MIPS_R6; if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) { env->CP0_Config5 |= (1 << CP0C5_FRE); |