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| author | Ben Widawsky <ben.widawsky@intel.com> | 2020-10-15 11:14:11 -0700 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2020-10-30 06:48:53 -0400 |
| commit | 6a5b19ca63b1795011f53244f2fd9a2cf8189b72 (patch) | |
| tree | 07be0522f584675c2589ecb11618eea0578d0028 /linux-user/mips/cpu_loop.c | |
| parent | 2c729dc8ceaab88f213c7724de0fa181ffc7f078 (diff) | |
| download | focaccia-qemu-6a5b19ca63b1795011f53244f2fd9a2cf8189b72.tar.gz focaccia-qemu-6a5b19ca63b1795011f53244f2fd9a2cf8189b72.zip | |
pci: Disallow improper BAR registration for type 1
Prevent future developers working on root complexes, root ports, or bridges that also wish to implement a BAR for those, from shooting themselves in the foot. PCI type 1 headers only support 2 base address registers. It is incorrect and difficult to figure out what is wrong with the device when this mistake is made. With this, it is immediate and obvious what has gone wrong. Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> Message-Id: <20201015181411.89104-2-ben.widawsky@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'linux-user/mips/cpu_loop.c')
0 files changed, 0 insertions, 0 deletions