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authorPhilipp Tomsich <philipp.tomsich@vrull.eu>2021-10-13 20:41:25 +0200
committerAlistair Francis <alistair@alistair23.me>2021-10-22 07:47:51 +1000
commit54c17609372bb119575f3bb7309ea57fc1a58d1d (patch)
tree5d2c58167fe5b22928be33172a2b723a3bd267d6 /linux-user/riscv/cpu_loop.c
parente573a7f325e4d66d1005f7bb80d51ce95f307951 (diff)
downloadfocaccia-qemu-54c17609372bb119575f3bb7309ea57fc1a58d1d.tar.gz
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target/riscv: Fix orc.b implementation
The earlier implementation fell into a corner case for bytes that were
0x01, giving a wrong result (but not affecting our application test
cases for strings, as an ASCII value 0x01 is rare in those...).

This changes the algorithm to:
 1. Mask out the high-bit of each bytes (so that each byte is <= 127).
 2. Add 127 to each byte (i.e. if the low 7 bits are not 0, this will overflow
    into the highest bit of each byte).
 3. Bitwise-or the original value back in (to cover those cases where the
    source byte was exactly 128) to saturate the high-bit.
 4. Shift-and-mask (implemented as a mask-and-shift) to extract the MSB of
    each byte into its LSB.
 5. Multiply with 0xff to fan out the LSB to all bits of each byte.

Fixes: d7a4fcb034 ("target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci")

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reported-by: Vincent Palatin <vpalatin@rivosinc.com>
Tested-by: Vincent Palatin <vpalatin@rivosinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211013184125.2010897-1-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'linux-user/riscv/cpu_loop.c')
0 files changed, 0 insertions, 0 deletions