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authorAlex Bennée <alex.bennee@linaro.org>2021-03-23 16:52:54 +0000
committerAlex Bennée <alex.bennee@linaro.org>2021-03-24 14:25:16 +0000
commit7967d1da7af01c49661241c47708caa6dec78adb (patch)
treeba0fd35327c3f9c7f9a52af8f56708924818c266 /linux-user/riscv/cpu_loop.c
parent35e3f029a966845e090dc8b295312751524df967 (diff)
downloadfocaccia-qemu-7967d1da7af01c49661241c47708caa6dec78adb.tar.gz
focaccia-qemu-7967d1da7af01c49661241c47708caa6dec78adb.zip
linux-user/riscv: initialise the TaskState heap/stack info
Arguably the target_cpu_copy_regs function for each architecture is
misnamed as a number of the architectures also take the opportunity to
fill out the TaskState structure. This could arguably be factored out
into common code but that would require a wider audit of the
architectures. For now just replicate for riscv so we can correctly
report semihosting information for SYS_HEAPINFO.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20210323165308.15244-9-alex.bennee@linaro.org>
Diffstat (limited to 'linux-user/riscv/cpu_loop.c')
-rw-r--r--linux-user/riscv/cpu_loop.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c
index 6767f941e8..74a9628dc9 100644
--- a/linux-user/riscv/cpu_loop.c
+++ b/linux-user/riscv/cpu_loop.c
@@ -135,4 +135,9 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
         error_report("Incompatible ELF: RVE cpu requires RVE ABI binary");
         exit(EXIT_FAILURE);
     }
+
+    ts->stack_base = info->start_stack;
+    ts->heap_base = info->brk;
+    /* This will be filled in on the first SYS_HEAPINFO call.  */
+    ts->heap_limit = 0;
 }