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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-01-07 13:32:33 -0800 |
|---|---|---|
| committer | Laurent Vivier <laurent@vivier.eu> | 2022-01-11 18:40:44 +0100 |
| commit | bf19bdb8f39a3aeb1353d412669b958c2b6cece8 (patch) | |
| tree | 72e51a12efdd3c06f69c3075ba9e8dbe096fe68c /linux-user/riscv/cpu_loop.c | |
| parent | 0b25c4a1f6345994d103ad08b2f4e1b366131dd9 (diff) | |
| download | focaccia-qemu-bf19bdb8f39a3aeb1353d412669b958c2b6cece8.tar.gz focaccia-qemu-bf19bdb8f39a3aeb1353d412669b958c2b6cece8.zip | |
linux-user/mips: Improve do_break
Rename to do_tr_or_bp, as per the kernel function. Add a 'trap' argument, akin to the kernel's si_code, but clearer. The return value is always 0, so change the return value to void. Use force_sig and force_sig_fault. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220107213243.212806-15-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Diffstat (limited to 'linux-user/riscv/cpu_loop.c')
0 files changed, 0 insertions, 0 deletions