diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2014-05-02 11:32:00 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-05-02 11:32:00 +0100 |
| commit | fdaad4715ae9e998fd0595bedfb16fdaf0c68ccc (patch) | |
| tree | 9bac96cfe44abbd7efa90780c63cbf2965efbfde /linux-user/signal.c | |
| parent | e50bf23438f8f35dcf32f9e720b04e0e969a3215 (diff) | |
| parent | f42c5c8ec8aa0e15583487ffee62964830751623 (diff) | |
| download | focaccia-qemu-fdaad4715ae9e998fd0595bedfb16fdaf0c68ccc.tar.gz focaccia-qemu-fdaad4715ae9e998fd0595bedfb16fdaf0c68ccc.zip | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140501' into staging
target-arm queue: * implement XScale cache lockdown cp15 ops * fix v7M CPUID base register * implement WFE and YIELD as yields for A64 * fix A64 "BLR LR" * support Cortex-A57 in virt machine model * a few other minor AArch64 bugfixes # gpg: Signature made Thu 01 May 2014 15:42:17 BST using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20140501: hw/arm/virt: Add support for Cortex-A57 hw/arm/virt: Put GIC register banks on 64K boundaries hw/arm/virt: Create the GIC ourselves rather than (ab)using a15mpcore_priv target-arm: Correct a comment refering to EL0 target-arm: A64: Fix a typo when declaring TLBI ops target-arm: A64: Handle blr lr target-arm: Make vbar_write 64bit friendly on 32bit hosts target-arm: implement WFE/YIELD as a yield for AArch64 armv7m_nvic: fix CPUID Base Register target-arm: Implement XScale cache lockdown operations as NOPs Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'linux-user/signal.c')
0 files changed, 0 insertions, 0 deletions