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| author | Peter Maydell <peter.maydell@linaro.org> | 2023-10-30 17:40:00 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-11-02 13:36:45 +0000 |
| commit | 854c001f121578c96b023b5db0c5550250505a0e (patch) | |
| tree | 462b14b36d0b5d715b1569a312e3886e949adc9f /linux-user/sparc/cpu_loop.c | |
| parent | 63c1b7de0a66e4ff248bdb51a0c3914de4eff034 (diff) | |
| download | focaccia-qemu-854c001f121578c96b023b5db0c5550250505a0e.tar.gz focaccia-qemu-854c001f121578c96b023b5db0c5550250505a0e.zip | |
target/arm: Make FEAT_MOPS SET* insns handle Xs == XZR correctly
Most of the registers used by the FEAT_MOPS instructions cannot use 31 as a register field value; this is CONSTRAINED UNPREDICTABLE to NOP or UNDEF (we UNDEF). However, it is permitted for the "source value" register for the memset insns SET* to be 31, which (as usual for most data-processing insns) means it should be the zero register XZR. We forgot to handle this case, with the effect that trying to set memory to zero with a "SET* Xd, Xn, XZR" sets the memory to the value that happens to be in the low byte of SP. Handle XZR when getting the SET* data value from the register file. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20231030174000.3792225-4-peter.maydell@linaro.org
Diffstat (limited to 'linux-user/sparc/cpu_loop.c')
0 files changed, 0 insertions, 0 deletions