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| author | Max Filippov <jcmvbkbc@gmail.com> | 2012-12-05 07:15:24 +0400 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2012-12-08 18:48:26 +0000 |
| commit | b7909d81f7658f64bba0faed83e7c2fd6a52fcba (patch) | |
| tree | 532268ec2f2f26c3321770fe23a4f7fab68cd6f5 /linux-user/sparc | |
| parent | 53593e90d13264dc88b3281ddf75ceaa641df05a (diff) | |
| download | focaccia-qemu-b7909d81f7658f64bba0faed83e7c2fd6a52fcba.tar.gz focaccia-qemu-b7909d81f7658f64bba0faed83e7c2fd6a52fcba.zip | |
target-xtensa: implement MISC SR
The Miscellaneous Special Registers Option provides zero to four scratch registers within the processor readable and writable by RSR, WSR, and XSR. These registers are privileged. They may be useful for some application-specific exception and interrupt processing tasks in the kernel. The MISC registers are undefined after reset. See ISA, 4.7.3 for details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'linux-user/sparc')
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