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| author | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-08-22 08:58:00 +0000 |
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| committer | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-08-22 08:58:00 +0000 |
| commit | 7da76bcef228adc68194eeeff07b00fc434a438c (patch) | |
| tree | 21b472ea444f134dfd9e3ae3808837baf53fb717 /linux-user/syscall.c | |
| parent | 06afe2c8840ec39c3b23db0eb830a5f49244b947 (diff) | |
| download | focaccia-qemu-7da76bcef228adc68194eeeff07b00fc434a438c.tar.gz focaccia-qemu-7da76bcef228adc68194eeeff07b00fc434a438c.zip | |
[sh4] code translation bug fix
When a TLB miss occurs while pre-decrement store instruction such as "mov.l Rm, @-Rn" is executed, re-execution of such instruction cause status confusion. Because pre Rn decrement is executed before TLB miss, re-execution decrements Rn again. In other words, in a translated instruction array, register status should not modified before memory access instruction. (Shin-ichiro KAWASAKI) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5069 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'linux-user/syscall.c')
0 files changed, 0 insertions, 0 deletions