Merge remote-tracking branch 'remotes/rth/tags/pull-tile-20150915' into staging

TileGX basic instructions

# gpg: Signature made Tue 15 Sep 2015 15:57:08 BST using RSA key ID 4DD0279B
# gpg: Good signature from "Richard Henderson <rth7680@gmail.com>"
# gpg:                 aka "Richard Henderson <rth@redhat.com>"
# gpg:                 aka "Richard Henderson <rth@twiddle.net>"

* remotes/rth/tags/pull-tile-20150915: (35 commits)
  target-tilegx: Handle v1shl, v1shru, v1shrs
  target-tilegx: Handle v1shli, v1shrui
  target-tilegx: Handle v4int_l/h
  target-tilegx: Handle atomic instructions
  target-tilegx: Handle mtspr, mfspr
  target-tilegx: Handle v1cmpeq, v1cmpne
  target-tilegx: Handle mask instructions
  target-tilegx: Handle scalar multiply instructions
  target-tilegx: Handle conditional move instructions
  target-tilegx: Handle shift instructions
  target-tilegx: Handle bitfield instructions
  target-tilegx: Implement system and memory management instructions
  target-tilegx: Handle comparison instructions
  target-tilegx: Handle conditional branch instructions
  target-tilegx: Handle unconditional jump instructions
  target-tilegx: Handle post-increment load and store instructions
  target-tilegx: Handle basic load and store instructions
  target-tilegx: Handle most bit manipulation instructions
  target-arm: Use new revbit functions
  host-utils: Add revbit functions
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

1 files changed, 40 insertions, 0 deletions

diff --git a/linux-user/tilegx/syscall.h b/linux-user/tilegx/syscall.h
new file mode 100644
index 0000000000..653ece13d8
--- /dev/null
+++ b/linux-user/tilegx/syscall.h
@@ -0,0 +1,40 @@
+#ifndef TILEGX_SYSCALLS_H
+#define TILEGX_SYSCALLS_H
+
+#define UNAME_MACHINE "tilegx"
+#define UNAME_MINIMUM_RELEASE "3.19"
+
+#define MMAP_SHIFT TARGET_PAGE_BITS
+
+#define TILEGX_IS_ERRNO(ret) \
+                       ((ret) > 0xfffffffffffff000ULL) /* errno is 0 -- 4096 */
+
+typedef uint64_t tilegx_reg_t;
+
+struct target_pt_regs {
+
+    union {
+        /* Saved main processor registers; 56..63 are special. */
+        tilegx_reg_t regs[56];
+        struct {
+            tilegx_reg_t __regs[53];
+            tilegx_reg_t tp;    /* aliases regs[TREG_TP] */
+            tilegx_reg_t sp;    /* aliases regs[TREG_SP] */
+            tilegx_reg_t lr;    /* aliases regs[TREG_LR] */
+        };
+    };
+
+    /* Saved special registers. */
+    tilegx_reg_t pc;            /* stored in EX_CONTEXT_K_0 */
+    tilegx_reg_t ex1;           /* stored in EX_CONTEXT_K_1 (PL and ICS bit) */
+    tilegx_reg_t faultnum;      /* fault number (INT_SWINT_1 for syscall) */
+    tilegx_reg_t orig_r0;       /* r0 at syscall entry, else zero */
+    tilegx_reg_t flags;         /* flags (see below) */
+    tilegx_reg_t cmpexch;       /* value of CMPEXCH_VALUE SPR at interrupt */
+    tilegx_reg_t pad[2];
+};
+
+#define TARGET_MLOCKALL_MCL_CURRENT 1
+#define TARGET_MLOCKALL_MCL_FUTURE  2
+
+#endif