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authorMax Filippov <jcmvbkbc@gmail.com>2017-01-25 10:54:11 -0800
committerMax Filippov <jcmvbkbc@gmail.com>2018-03-16 09:40:34 -0700
commitba7651fba54199e5dedbbd08157687291b9dbae3 (patch)
treef03b970e3cfdfde9040ff14c59dc0bf3acfb6fe3 /linux-user/xtensa/target_syscall.h
parentbf9c3a5a96dfabcdcb7964110866bb9bc06a43c1 (diff)
downloadfocaccia-qemu-ba7651fba54199e5dedbbd08157687291b9dbae3.tar.gz
focaccia-qemu-ba7651fba54199e5dedbbd08157687291b9dbae3.zip
target/xtensa: add linux-user support
Import list of syscalls from the kernel source. Conditionalize code/data
that is only used with softmmu. Implement exception handlers. Implement
signal hander (only the core registers for now, no coprocessors or TIE).

Cc: Riku Voipio <riku.voipio@iki.fi>
Cc: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'linux-user/xtensa/target_syscall.h')
-rw-r--r--linux-user/xtensa/target_syscall.h49
1 files changed, 49 insertions, 0 deletions
diff --git a/linux-user/xtensa/target_syscall.h b/linux-user/xtensa/target_syscall.h
new file mode 100644
index 0000000000..3866dad849
--- /dev/null
+++ b/linux-user/xtensa/target_syscall.h
@@ -0,0 +1,49 @@
+#ifndef XTENSA_TARGET_SYSCALL_H
+#define XTENSA_TARGET_SYSCALL_H
+
+#define UNAME_MACHINE "xtensa"
+
+#define UNAME_MINIMUM_RELEASE "3.19"
+#define TARGET_CLONE_BACKWARDS
+
+#define MMAP_SHIFT TARGET_PAGE_BITS
+
+typedef uint32_t xtensa_reg_t;
+typedef struct {
+} xtregs_opt_t; /* TODO */
+
+struct target_pt_regs {
+    xtensa_reg_t pc;            /*   4 */
+    xtensa_reg_t ps;            /*   8 */
+    xtensa_reg_t depc;          /*  12 */
+    xtensa_reg_t exccause;      /*  16 */
+    xtensa_reg_t excvaddr;      /*  20 */
+    xtensa_reg_t debugcause;    /*  24 */
+    xtensa_reg_t wmask;         /*  28 */
+    xtensa_reg_t lbeg;          /*  32 */
+    xtensa_reg_t lend;          /*  36 */
+    xtensa_reg_t lcount;        /*  40 */
+    xtensa_reg_t sar;           /*  44 */
+    xtensa_reg_t windowbase;    /*  48 */
+    xtensa_reg_t windowstart;   /*  52 */
+    xtensa_reg_t syscall;       /*  56 */
+    xtensa_reg_t icountlevel;   /*  60 */
+    xtensa_reg_t scompare1;     /*  64 */
+    xtensa_reg_t threadptr;     /*  68 */
+
+    /* Additional configurable registers that are used by the compiler. */
+    xtregs_opt_t xtregs_opt;
+
+    /* Make sure the areg field is 16 bytes aligned. */
+    int align[0] __attribute__ ((aligned(16)));
+
+    /* current register frame.
+     * Note: The ESF for kernel exceptions ends after 16 registers!
+     */
+    xtensa_reg_t areg[16];
+};
+
+#define TARGET_MLOCKALL_MCL_CURRENT 1
+#define TARGET_MLOCKALL_MCL_FUTURE  2
+
+#endif