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authorPeter Maydell <peter.maydell@linaro.org>2022-04-04 15:48:55 +0100
committerPeter Maydell <peter.maydell@linaro.org>2022-04-04 15:48:55 +0100
commit20661b75ea6093f5e59079d00a778a972d6732c5 (patch)
treed1b7b85ec58e7b624a28f23303afd1c129907fa9 /linux-user
parentbc6ec396d471d9e4aae7e2ff8b72e11da9a97665 (diff)
parent0798da8df9fd917515c957ae918d6d979cf5f3fb (diff)
downloadfocaccia-qemu-20661b75ea6093f5e59079d00a778a972d6732c5.tar.gz
focaccia-qemu-20661b75ea6093f5e59079d00a778a972d6732c5.zip
Merge tag 'pull-ppc-20220404' of https://github.com/legoater/qemu into staging
ppc-7.0 queue:

* Coverity fixes
* Fix for a memory leak issue

# gpg: Signature made Mon 04 Apr 2022 09:45:51 BST
# gpg:                using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B  0B60 51A3 43C7 CFFB ECA1

* tag 'pull-ppc-20220404' of https://github.com/legoater/qemu:
  linux-user/ppc: Narrow type of ccr in save_user_regs
  ppc/pnv: Fix number of registers in the PCIe controller on POWER9
  hw/ppc: free env->tb_env in spapr_unrealize_vcpu()

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'linux-user')
-rw-r--r--linux-user/ppc/signal.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/linux-user/ppc/signal.c b/linux-user/ppc/signal.c
index ec0b9c0df3..ce5a4682cd 100644
--- a/linux-user/ppc/signal.c
+++ b/linux-user/ppc/signal.c
@@ -229,7 +229,7 @@ static void save_user_regs(CPUPPCState *env, struct target_mcontext *frame)
 {
     target_ulong msr = env->msr;
     int i;
-    target_ulong ccr = 0;
+    uint32_t ccr = 0;
 
     /* In general, the kernel attempts to be intelligent about what it
        needs to save for Altivec/FP/SPE registers.  We don't care that