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| author | Kito Cheng <kito.cheng@gmail.com> | 2019-03-26 17:27:17 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-03-26 03:17:30 -0700 |
| commit | 620455350a8da7cc62ae82cb69dd5c556f744136 (patch) | |
| tree | d6fa9ea50e3a9e1d2361869b8273881fdfdaa9df /net/socket.c | |
| parent | 4aef51963924fd58ffe88daebbe8055a360d7c10 (diff) | |
| download | focaccia-qemu-620455350a8da7cc62ae82cb69dd5c556f744136.tar.gz focaccia-qemu-620455350a8da7cc62ae82cb69dd5c556f744136.zip | |
target/riscv: Fix wrong expanding for c.fswsp
base register is no rs1 not rs2 for fsw. Signed-off-by: Kito Cheng <kito.cheng@gmail.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'net/socket.c')
0 files changed, 0 insertions, 0 deletions