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| author | Yongbok Kim <yongbok.kim@mips.com> | 2018-10-09 18:15:46 +0200 |
|---|---|---|
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | 2018-10-18 20:37:20 +0200 |
| commit | fa75ad1459f4f6abbeb6d375a812dfad61320f58 (patch) | |
| tree | 87f3a29e0eee3cf26255f84e18624990ac0c1ef7 /net/socket.c | |
| parent | 5e31fdd59fda5c4ba9eb0daadc2a26273a29a0b6 (diff) | |
| download | focaccia-qemu-fa75ad1459f4f6abbeb6d375a812dfad61320f58.tar.gz focaccia-qemu-fa75ad1459f4f6abbeb6d375a812dfad61320f58.zip | |
target/mips: Add CP0 PWField register
Add PWField register (CP0 Register 5, Select 6). The PWField register configures hardware page table walking for TLB refills. This register is required for the hardware page walker feature. It exists only if Config3 PW bit is set to 1. It contains following fields: MIPS64: BDI (37..32) - Base Directory index GDI (29..24) - Global Directory index UDI (23..18) - Upper Directory index MDI (17..12) - Middle Directory index PTI (11..6 ) - Page Table index PTEI ( 5..0 ) - Page Table Entry shift MIPS32: GDW (29..24) - Global Directory index UDW (23..18) - Upper Directory index MDW (17..12) - Middle Directory index PTW (11..6 ) - Page Table index PTEW ( 5..0 ) - Page Table Entry shift Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Diffstat (limited to 'net/socket.c')
0 files changed, 0 insertions, 0 deletions