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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-05-14 14:28:26 -0700 |
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| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-06-05 17:23:09 +0100 |
| commit | a04b68e1d4c4f0cd5cd7542697b1b230b84532f5 (patch) | |
| tree | be6fadf55ef1bba13499d60949ccd2ec14174f2d /python/qemu/accel.py | |
| parent | fc417e5b5784eec92163ad36140ab029c6661b5f (diff) | |
| download | focaccia-qemu-a04b68e1d4c4f0cd5cd7542697b1b230b84532f5.tar.gz focaccia-qemu-a04b68e1d4c4f0cd5cd7542697b1b230b84532f5.zip | |
target/arm: Convert aes and sm4 to gvec helpers
With this conversion, we will be able to use the same helpers with sve. In particular, pass 3 vector parameters for the 3-operand operations; for advsimd the destination register is also an input. This also fixes a bug in which we failed to clear the high bits of the SVE register after an AdvSIMD operation. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200514212831.31248-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'python/qemu/accel.py')
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