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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-10-12 11:57:52 +0200 |
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| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-10-17 11:13:15 +0200 |
| commit | 68b981aa76079216f5765a6aecaf8728f27d3696 (patch) | |
| tree | 51e21fb183ef004f55767fc8c8e57ab72b77dbd3 /python/qemu/console_socket.py | |
| parent | d225b5122029c3d6293aab6e2d0a05597fc92ba4 (diff) | |
| download | focaccia-qemu-68b981aa76079216f5765a6aecaf8728f27d3696.tar.gz focaccia-qemu-68b981aa76079216f5765a6aecaf8728f27d3696.zip | |
target/mips/cpu: Calculate the CP0 timer period using the CPU frequency
The CP0 timer period is a function of the CPU frequency. Start using the default values, which will be replaced by properties in the next commits. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20201012095804.3335117-10-f4bug@amsat.org>
Diffstat (limited to 'python/qemu/console_socket.py')
0 files changed, 0 insertions, 0 deletions