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| author | Jiaxun Yang <jiaxun.yang@flygoat.com> | 2020-10-16 14:51:56 +0800 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-10-17 11:13:15 +0200 |
| commit | 90e22a57af975dea08b3015dfac072709f131616 (patch) | |
| tree | b2bbfebf357259869945f7194d93e11fc738a3a9 /python/qemu/console_socket.py | |
| parent | fd723105c15e09b8a9eaad29fa59347e63cfdb20 (diff) | |
| download | focaccia-qemu-90e22a57af975dea08b3015dfac072709f131616.tar.gz focaccia-qemu-90e22a57af975dea08b3015dfac072709f131616.zip | |
target/mips: Add loongson-ext lsdc2 group of instructions
LDC2/SDC2 opcodes have been rewritten as "load & store with offset" group of instructions by loongson-ext ASE. This patch add implementation of these instructions: gslbx: load 1 bytes to GPR gslhx: load 2 bytes to GPR gslwx: load 4 bytes to GPR gsldx: load 8 bytes to GPR gslwxc1: load 4 bytes to FPR gsldxc1: load 8 bytes to FPR gssbx: store 1 bytes from GPR gsshx: store 2 bytes from GPR gsswx: store 4 bytes from GPR gssdx: store 8 bytes from GPR gsswxc1: store 4 bytes from FPR gssdxc1: store 8 bytes from FPR Details of Loongson-EXT is here: https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhc@lemote.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1602831120-3377-5-git-send-email-chenhc@lemote.com>
Diffstat (limited to 'python/qemu/console_socket.py')
0 files changed, 0 insertions, 0 deletions