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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-03-01 11:59:47 -1000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-03-02 19:27:36 +0000 |
| commit | f4ecc01537684a4125c35433f3097295d0a1f839 (patch) | |
| tree | ef4829b288da0e4c5332e58e34b95f4adcb4b33a /python/qemu/machine/console_socket.py | |
| parent | d06449f2eb555896057ee047b3009a3616d52028 (diff) | |
| download | focaccia-qemu-f4ecc01537684a4125c35433f3097295d0a1f839.tar.gz focaccia-qemu-f4ecc01537684a4125c35433f3097295d0a1f839.zip | |
target/arm: Honor TCR_ELx.{I}PS
This field controls the output (intermediate) physical address size of the translation process. V8 requires to raise an AddressSize fault if the page tables are programmed incorrectly, such that any intermediate descriptor address, or the final translated address, is out of range. Add a PS field to ARMVAParameters, and properly compute outputsize in get_phys_addr_lpae. Test the descaddr as extracted from TTBR and from page table entries. Restrict descaddrmask so that we won't raise the fault for v7. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220301215958.157011-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'python/qemu/machine/console_socket.py')
0 files changed, 0 insertions, 0 deletions