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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2022-11-01 23:29:33 +0100 |
|---|---|---|
| committer | Daniel Henrique Barboza <danielhb413@gmail.com> | 2022-12-21 14:17:55 -0300 |
| commit | c0a55a0c9da2ffd7836530f9b30171eef3da03b7 (patch) | |
| tree | 9e4d75e0ee521a53e22c5f0b884a63c018d6a1cb /python/qemu/machine/machine.py | |
| parent | 2e93a90f4f0ea0503c1a850b2ea04e5eb8063e8c (diff) | |
| download | focaccia-qemu-c0a55a0c9da2ffd7836530f9b30171eef3da03b7.tar.gz focaccia-qemu-c0a55a0c9da2ffd7836530f9b30171eef3da03b7.zip | |
hw/sd/sdhci: Support big endian SD host controller interfaces
Some SDHCI IP can be synthetized in various endianness:
https://github.com/u-boot/u-boot/blob/v2021.04/doc/README.fsl-esdhc
- CONFIG_SYS_FSL_ESDHC_BE
ESDHC IP is in big-endian mode. Accessing ESDHC registers can be
determined by ESDHC IP's endian mode or processor's endian mode.
Our current implementation is little-endian. In order to support
big endianness:
- Rename current MemoryRegionOps as sdhci_mmio_le_ops ('le')
- Add an 'endianness' property to SDHCIState (default little endian)
- Set the 'io_ops' field in realize() after checking the property
- Add the sdhci_mmio_be_ops (big-endian) MemoryRegionOps.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20221101222934.52444-3-philmd@linaro.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'python/qemu/machine/machine.py')
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