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authorRichard Henderson <richard.henderson@linaro.org>2021-11-17 10:51:29 +0100
committerRichard Henderson <richard.henderson@linaro.org>2021-11-17 10:51:29 +0100
commit52cebbfc133fb784644edeae1e5b53aac3b64e5f (patch)
tree74b27b822e26a5690a23659fbe1e93d5418bfcc7 /python/qemu/machine
parent8d5fcb1990bc64b62c0bc12121fe510940be5664 (diff)
parentc94c239496256f1f1cb589825d052c2f3e26ebf6 (diff)
downloadfocaccia-qemu-52cebbfc133fb784644edeae1e5b53aac3b64e5f.tar.gz
focaccia-qemu-52cebbfc133fb784644edeae1e5b53aac3b64e5f.zip
Merge tag 'pull-riscv-to-apply-20211117-1' of github.com:alistair23/qemu into staging
Sixth RISC-V PR for QEMU 6.2

 - Fix build for riscv hosts
 - Soft code alphabetically

# gpg: Signature made Wed 17 Nov 2021 10:19:25 AM CET
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]

* tag 'pull-riscv-to-apply-20211117-1' of github.com:alistair23/qemu:
  meson.build: Merge riscv32 and riscv64 cpu family
  target/riscv: machine: Sort the .subsections

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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