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| author | Peter Maydell <peter.maydell@linaro.org> | 2020-10-19 16:12:59 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-10-20 16:12:01 +0100 |
| commit | 532a3af5fbd348bca371b4a56b45f8f97c7c5519 (patch) | |
| tree | d4dd8f99b461632a132129d2e7a9ff8109aa21b3 /python/qemu/qmp.py | |
| parent | b7226369721896ab9ef71544e4fe95b40710e05a (diff) | |
| download | focaccia-qemu-532a3af5fbd348bca371b4a56b45f8f97c7c5519.tar.gz focaccia-qemu-532a3af5fbd348bca371b4a56b45f8f97c7c5519.zip | |
target/arm: Fix has_vfp/has_neon ID reg squashing for M-profile
In arm_cpu_realizefn(), if the CPU has VFP or Neon disabled then we squash the ID register fields so that we don't advertise it to the guest. This code was written for A-profile and needs some tweaks to work correctly on M-profile: * A-profile only fields should not be zeroed on M-profile: - MVFR0.FPSHVEC,FPTRAP - MVFR1.SIMDLS,SIMDINT,SIMDSP,SIMDHP - MVFR2.SIMDMISC * M-profile only fields should be zeroed on M-profile: - MVFR1.FP16 In particular, because MVFR1.SIMDHP on A-profile is the same field as MVFR1.FP16 on M-profile this code was incorrectly disabling FP16 support on an M-profile CPU (where has_neon is always false). This isn't a visible bug yet because we don't have any M-profile CPUs with FP16 support, but the change is necessary before we introduce any. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20201019151301.2046-9-peter.maydell@linaro.org
Diffstat (limited to 'python/qemu/qmp.py')
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