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| author | Luc Michel <luc.michel@amd.com> | 2025-09-26 09:07:33 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2025-10-07 10:35:36 +0100 |
| commit | 060b809271f9d0d6205fe2232d0aead4a37fa0e7 (patch) | |
| tree | 409a530a2721fc421e8a8b0f8fd175e65ec013e4 /python/qemu/utils/accel.py | |
| parent | c58d45a2b9d62638b94cc003c61603f5030dcba7 (diff) | |
| download | focaccia-qemu-060b809271f9d0d6205fe2232d0aead4a37fa0e7.tar.gz focaccia-qemu-060b809271f9d0d6205fe2232d0aead4a37fa0e7.zip | |
hw/arm/xlnx-versal: trng: refactor creation
Refactor the TRNG device creation using the VersalMap structure. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-16-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'python/qemu/utils/accel.py')
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