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| author | WANG Xuerui <git@xen0n.name> | 2021-12-21 13:40:39 +0800 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2021-12-21 13:17:06 -0800 |
| commit | 1bcfbf03dfa38c727312166081c0921590e798be (patch) | |
| tree | 73ca2975b481f3a49369355aa717d98cf07e4055 /python/qemu/utils/accel.py | |
| parent | 71bb0283f5734053a962feac42f20ab70c370f28 (diff) | |
| download | focaccia-qemu-1bcfbf03dfa38c727312166081c0921590e798be.tar.gz focaccia-qemu-1bcfbf03dfa38c727312166081c0921590e798be.zip | |
tcg/loongarch64: Add register names, allocation order and input/output sets
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211221054105.178795-6-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'python/qemu/utils/accel.py')
0 files changed, 0 insertions, 0 deletions