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authorLawrence Hunter <lawrence.hunter@codethink.co.uk>2023-07-12 00:59:10 +0800
committerAlistair Francis <alistair.francis@wdc.com>2023-09-11 11:45:55 +1000
commit2350881c44bdc7c72de6525dbfadddb93ebfd146 (patch)
treec653f00e57aab9008fb2ee71512567211bd27b77 /python/qemu/utils/accel.py
parentfcf1943376a50a26382143da5f886609c0619d44 (diff)
downloadfocaccia-qemu-2350881c44bdc7c72de6525dbfadddb93ebfd146.tar.gz
focaccia-qemu-2350881c44bdc7c72de6525dbfadddb93ebfd146.zip
target/riscv: Add Zvksh ISA extension support
This commit adds support for the Zvksh vector-crypto extension, which
consists of the following instructions:

* vsm3me.vv
* vsm3c.vi

Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.

Co-authored-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
[max.chou@sifive.com: Replaced vstart checking by TCG op]
Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
[max.chou@sifive.com: Exposed x-zvksh property]
Message-ID: <20230711165917.2629866-12-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'python/qemu/utils/accel.py')
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