diff options
| author | Atish Patra <atishp@rivosinc.com> | 2022-03-03 10:54:39 -0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-04-22 10:35:16 +1000 |
| commit | 29a9ec9bd8a7a7a4d98aa9a2260db6b2e815fb77 (patch) | |
| tree | 607eadf2628526052f15eb202a9528f927a8c0dc /python/qemu/utils/accel.py | |
| parent | 3e6a417c8a077595ebcb4fb1d0944b291564cd43 (diff) | |
| download | focaccia-qemu-29a9ec9bd8a7a7a4d98aa9a2260db6b2e815fb77.tar.gz focaccia-qemu-29a9ec9bd8a7a7a4d98aa9a2260db6b2e815fb77.zip | |
target/riscv: Add *envcfg* CSRs support
The RISC-V privileged specification v1.12 defines few execution environment configuration CSRs that can be used enable/disable extensions per privilege levels. Add the basic support for these CSRs. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220303185440.512391-6-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'python/qemu/utils/accel.py')
0 files changed, 0 insertions, 0 deletions