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authorMatheus Ferst <matheus.ferst@eldorado.org.br>2021-11-04 09:37:01 -0300
committerDavid Gibson <david@gibson.dropbear.id.au>2021-11-09 10:32:52 +1100
commit2c9f79584107313e880995ffd2b36f6d28b7bc2e (patch)
tree467c1da41d4d643766d1e32873c0a0fea3c53c2a /python/qemu/utils/accel.py
parent23832ae6d53a25e3a56f103fcba55ead17e8e0cf (diff)
downloadfocaccia-qemu-2c9f79584107313e880995ffd2b36f6d28b7bc2e.tar.gz
focaccia-qemu-2c9f79584107313e880995ffd2b36f6d28b7bc2e.zip
target/ppc: Implement Vector Insert from VSR using GPR index insns
Implements the following PowerISA v3.1 instructions:
vinsbvlx: Vector Insert Byte from VSR using GPR-specified Left-Index
vinshvlx: Vector Insert Halfword from VSR using GPR-specified
          Left-Index
vinswvlx: Vector Insert Word from VSR using GPR-specified Left-Index
vinsbvrx: Vector Insert Byte from VSR using GPR-specified Right-Index
vinshvrx: Vector Insert Halfword from VSR using GPR-specified
          Right-Index
vinswvrx: Vector Insert Word from VSR using GPR-specified Right-Index

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211104123719.323713-8-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'python/qemu/utils/accel.py')
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