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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-06-17 13:15:46 +0100 |
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| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-06-21 16:49:38 +0100 |
| commit | 2fc6b7510c6859478264b7402ba01dbee86b7e46 (patch) | |
| tree | 3ab48286e845fc2af5136b963b407f19294857bb /python/qemu/utils/accel.py | |
| parent | 507b6a500c2f0f6cf6182aa69efac4c20eb3e97b (diff) | |
| download | focaccia-qemu-2fc6b7510c6859478264b7402ba01dbee86b7e46.tar.gz focaccia-qemu-2fc6b7510c6859478264b7402ba01dbee86b7e46.zip | |
target/arm: Implement widening/narrowing MVE VLDR/VSTR insns
Implement the variants of MVE VLDR (encodings T1, T2) which perform "widening" loads where bytes or halfwords are loaded from memory and zero or sign-extended into halfword or word length vector elements, and the narrowing MVE VSTR (encodings T1, T2) where bytes or halfwords are stored from halfword or word elements. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-3-peter.maydell@linaro.org
Diffstat (limited to 'python/qemu/utils/accel.py')
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