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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-06-17 13:16:11 +0100 |
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| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-06-24 14:58:47 +0100 |
| commit | 39f2ec8592dd3c823034dc4decc64c7e4cc42bfd (patch) | |
| tree | e0d566b654bdb3220038ee5d7a90f94e36c007ec /python/qemu/utils/accel.py | |
| parent | 387debdb93d2635fb6d62bff38887d17ef4d8117 (diff) | |
| download | focaccia-qemu-39f2ec8592dd3c823034dc4decc64c7e4cc42bfd.tar.gz focaccia-qemu-39f2ec8592dd3c823034dc4decc64c7e4cc42bfd.zip | |
target/arm: Implement MVE VQADD and VQSUB
Implement the MVE VQADD and VQSUB insns, which perform saturating addition of a scalar to each element. Note that individual bytes of each result element are used or discarded according to the predicate mask, but FPSCR.QC is only set if the predicate mask for the lowest byte of the element is set. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-28-peter.maydell@linaro.org
Diffstat (limited to 'python/qemu/utils/accel.py')
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