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| author | Cédric Le Goater <clg@kaod.org> | 2022-03-23 08:28:42 +0100 |
|---|---|---|
| committer | Daniel Henrique Barboza <danielhb413@gmail.com> | 2022-04-20 18:00:30 -0300 |
| commit | 58858759c198dc56498095e387a31178d0d852b9 (patch) | |
| tree | a8002544b3d7c7bb5ee85eca591616b76cb88f28 /python/qemu/utils/accel.py | |
| parent | 4c7daca302a4f4d0f66f1112e094307863c4f6c8 (diff) | |
| download | focaccia-qemu-58858759c198dc56498095e387a31178d0d852b9.tar.gz focaccia-qemu-58858759c198dc56498095e387a31178d0d852b9.zip | |
ppc/pnv: Fix PSI IRQ definition
On HW, the PSI and FSP interrupt levels are muxed under the same interrupt number. For coding reasons, an extra IRQ number was introduced to index register values in an array. It increased the count of IRQs which do not fit in the PSI IRQ range anymore. The PSI and FSP interrupts should be modeled with an extra level of GPIO lines but since QEMU does not support them, simply drop the extra number to stay within the IRQ range. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220323072846.1780212-2-clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'python/qemu/utils/accel.py')
0 files changed, 0 insertions, 0 deletions