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authorPeter Maydell <peter.maydell@linaro.org>2022-04-08 15:15:38 +0100
committerPeter Maydell <peter.maydell@linaro.org>2022-04-22 14:44:53 +0100
commit6631480c9a9c3864d235b811dfc1ceb95a663662 (patch)
treeed69349e9d17227f380f096d187aa8490840eee5 /python/qemu/utils/accel.py
parent99ba56d25beb3962c2f876690fe429d817cb7b06 (diff)
downloadfocaccia-qemu-6631480c9a9c3864d235b811dfc1ceb95a663662.tar.gz
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hw/intc/arm_gicv3_redist: Recalculate hppvlpi on VPENDBASER writes
The guest uses GICR_VPENDBASER to tell the redistributor when it is
scheduling or descheduling a vCPU.  When it writes and changes the
VALID bit from 0 to 1, it is scheduling a vCPU, and we must update
our view of the current highest priority pending vLPI from the new
Pending and Configuration tables.  When it writes and changes the
VALID bit from 1 to 0, it is descheduling, which means that there is
no longer a highest priority pending vLPI.

The specification allows the implementation to use part of the vLPI
Pending table as an IMPDEF area where it can cache information when a
vCPU is descheduled, so that it can avoid having to do a full rescan
of the tables when the vCPU is scheduled again.  For now, we don't
take advantage of this, and simply do a complete rescan.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-30-peter.maydell@linaro.org
Diffstat (limited to 'python/qemu/utils/accel.py')
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